1. Field of the Invention
The present invention relates to the manufacturing in monolithic form of DRAM cells. More specifically, the present invention relates to the manufacturing on the same semiconductor wafer of DRAM cells and of MOS transistors according to a process compatible with a standard CMOS process.
2. Discussion of the Related Art
FIG. 1 shows an example of a wafer structure on which are formed DRAM cells and MOS transistors according to a conventional CMOS process. DRAM cells (a single cell being formed), each of which is formed of a MOS control transistor and of a capacitor, a first electrode of the capacitor being in contact with the drain or source region of the transistor, are formed to the right of FIG. 1, on a first portion of a semiconductor substrate 11. On a second portion of substrate 11, to the left of the drawing, logic circuits including MOS transistors are formed. Hereafter, the first and second portions will be called the memory side and the logic side. It should be noted that xe2x80x9csubstratexe2x80x9d designates the actual substrate as well the wells and/or doped regions formed therein. It should also be noted that, on the logic side, no MOS transistor gates have been formed.
The manufacturing method of this conventional structure is the following. The MOS transistors 15 on the memory side and on the logic side are first formed. Each MOS transistor 15 includes doped source and drain regions 16 and an associated gate 17. Each gate 17 is formed of a multiple-layer: a gate insulator 18 in contact with semiconductor substrate 11, a polysilicon layer 19, and a conductive layer 20, for example, CoSi2 (connected to a gate, not shown). Spacers 21, for example, Si3N4, are arranged on either side of gate 17. The gate structure is optimized mainly with a view to the desired properties of the transistors located on the logic side.
A protection layer 22, for example, silicon oxynitride (SiON), is deposited on the structure thus obtained. A first insulating layer 23 is then deposited on the memory side and on the logic side. First vias 25, for example, made of tungsten, which cross first insulating layer 23 and protection layer 22 to contact source or drain regions 16, are formed on the memory side and on the logic side.
A second insulating layer 26 is then deposited on the memory side and on the logic side.
On the memory side, openings 30 having a width substantially corresponding to the pitch of the gates crossing second insulating layer 26 are etched to expose the upper ends of first vias 25 not connected to second vias 35.
The capacitors are then formed. The walls of openings 30 are covered with a first conductive material 31 which forms the first capacitor electrode. A dielectric 32 covers first conductive material 31 and forms the second capacitor electrode. A second conductive material 33 covers dielectric 32 and forms the second capacitor electrode.
A third insulating layer 34 is deposited on the memory side and on the logic side. Second vias 35, for example, made of tungsten, which cross the second and third insulating layers 26, 34 to join, on the logic side, all first vias 25, and to join, on the memory side, some of first vias 25, are formed on the memory side and on the logic side. Vias 36 which cross third insulating layer 34 to contact second conductive material 33 of the capacitors are also formed.
Contacts 37 of vias 35, on the logic side, and contacts of vias 35 and 36, on the memory side, are finally formed in third insulating layer 34.
Second vias 35, for example, made of tungsten, which cross second insulating layer 26 to join, on the logic side, all first vias 25, and to join, on the memory side, some of first vias 25, are formed on the memory side and on the logic side.
For such a structure, the spacing between transistors being mainly imposed by the CMOS process being used, the dimensions of the capacitors and thus their capacitance, are a direct function of the thickness of second insulating layer 26. To increase the capacitance of the capacitors, it could be attempted to increase the thickness of second insulating layer 26.
However, this increase is necessarily limited. Indeed, generally, it is desired to form vias having the smallest possible diameter, and those skilled in the art know that the forming of vias of small diameter in an insulating layer of high thickness is difficult. Indeed, it is difficult to fill an opening of small diameter with a conductive material to ensure a satisfactory electric connection. The ratio between the thickness of the insulating layer and the diameter of the opening in which the via must be formed is called the aspect ratio. The higher this ratio, the more difficult is the realization of the via. For vias having a 200-nm diameter, according to current technologies, maximum aspect ratios on the order of 9 may be reached, which limits the thickness of the second layer to values on the order of 1800 nm.
Thus, the DRAM manufacturing method using gate structures and metal vias compatible with a conventional CMOS technology imposes a limit to the increase in the capacitance of memory cell capacitors.
FIG. 2 shows an example of a DRAM cell structure formed in a semiconductor wafer by a method aiming at optimizing the manufacturing of these cells, possibly to the detriment of simultaneously-formed CMOS logic circuits.
The method for manufacturing such a memory cell is the following. MOS transistors 51 including source and drain regions 52 formed in a semiconductor substrate 53 are first formed. The gates associated with MOS transistors 51 are formed of a multiple layer formed of a gate insulator 54, of a polysilicon layer 55, of a conductive layer, for example, tungsten silicide (WSix) 56, and of an insulating layer, for example, Si3N4, 57. Spacers 58, for example, Si3N4, are formed on either side of the gate.
Then, a protection layer 59, for example, SiON, and an insulating layer 60, are deposited over the entire structure.
Insulating layer 60 and protection layer 59 are etched to form openings 61 exposing source and drain regions 52, the etch stop being obtained by spacers 58 and Si3N4 insulating layer 57. The capacitor is then formed.
The capacitors are finally formed, conventionally, in openings 61. The walls of openings 61 are covered with a first conductive material 62 which forms the first capacitor electrode. A dielectric 63 covers first conductive material 62. A second conductive material 64 covers dielectric 63 and forms the second capacitor electrode.
Such a capacitor structure, for which the capacitor extends over the entire thickness of insulating layer 60, enables making the facing surface area between the two capacitor electrodes maximum. It is an optimal structure to obtain a capacitor of maximum capacitance.
It is however not possible to reproduce this structure when memory cells and MOS transistors are desired to be formed on the same wafer according to a conventional CMOS process.
Indeed, in the case of a manufacturing on a same wafer of DRAM cells and of MOS transistors, an optimal structure for the MOS transistors located on the logic side is generally chosen, this structure being reproduced for the memory cell control transistors. As a result, the transistor structure may not be optimal for the memory cells. Thus, it appears that the multiple-layer forming gate 17 of a MOS transistor of FIG. 1 has a structure different from that of the gate of a MOS transistor of FIG. 2. Indeed, in FIG. 1, polysilicon layer 19 is only covered with a conductive layer 20, while in FIG. 2, polysilicon layer 55 is covered with a conductive layer 56 and with an Si3N4 insulating layer 57. The gates further are, on both drawings, covered with a protection layer 22, 59, for example, SiON.
Accordingly, with the transistor structure of FIG. 1, if the openings in which the capacitors will be formed are etched to reach the level of the MOS transistor gates, protection layer 22 covering the gates will be etched. In the capacitor forming, short-circuits will be obtained between the conductive material of the capacitors and the upper conductive layers of the gates.
The present invention accordingly aims at providing a novel manufacturing method of DRAM cells and MOS transistors in a same integrated circuit wafer enabling obtaining an optimal capacitor capacitance while remaining compatible with standard transistor gate structures.
The present invention also aims at providing a method for forming vias having an improved aspect ratio.
To achieve these and other objects, the present invention provides a method for manufacturing, in a first region of a semiconductor wafer, DRAM cells each including a MOS control transistor and a capacitor and, in a second region of the wafer, MOS transistors, the first and second regions being covered with a protection layer and with a first insulating layer, including the steps of etching at the level of the first region first openings to expose the source or drain regions of the control transistors; filling the first openings with a first conductive material; re-etching the first conductive material down to part of the depth of the first openings; depositing at the level of the first and second regions a second insulating layer; etching at the level of the first region second openings and at the level of the second region third openings exposing source or drain regions of the transistors; and filling the second and third openings with a second conductive material; depositing at the level of the first and second regions a third insulating layer; etching at the level of the first region fourth openings exposing the first conductive material of the first openings, and extending over gates of adjacent control transistors; forming the capacitors at the level of the fourth openings; and etching at the level of the first and second regions fifth openings respectively joining the second openings and the third openings; and filling the fifth openings of the second conductive material to form vias.
According to another embodiment of the present invention, the protection layer covering the gates of the control transistors forms an etch stop upon etching of the fourth openings.
According to another embodiment of the present invention, the second openings expose the first conductive material of first openings.
According to another embodiment of the present invention, the second openings expose source or drain regions of the control transistors.
According to another embodiment of the present invention, the capacitor is formed by covering the walls and the bottom of the fourth openings with a third conductive material forming the first capacitor electrode, then depositing a dielectric material forming a capacitor insulator, and depositing a fourth conductive material forming a second capacitor electrode.
According to another embodiment of the present invention, the first conductive material is polysilicon.
According to another embodiment of the present invention, the second conductive material is a metal or a metal nitride.
According to another embodiment of the present invention, the protection layer is a multiple-layer.
According to another embodiment of the present invention, the protection layer includes Si3N4.
The foregoing embodiments, features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.